As computers have grown in complexity, the demand for more memory has grown. This in turn has led to a greater demand for higher density memories (memories capable of storing more bits of information in the same semiconductor surface area). In an attempt to increase the storage density of memories, the concept of a multi-bit memory cell was developed. More specifically, it was envisioned that if each memory cell were able to store more than one bit of data, then the storage density of the memory would be increased. Consequently, efforts have been made in recent years to develop memories using multi-bit memory cells. Most of the multi-bit memory cell work has been done in connection with DRAM memory cells.
In general, a multi-bit DRAM cell has the same construction as a single-bit DRAM cell, consisting of a storage capacitor and a cell gate. The difference between the multi-bit cell and the single-bit cell is manitested in the way the cells are used. To illustrate how a single memory cell can be used to store a plurality of bits of data, suppose that it is desirable to store two bits of data in a memory cell, and that the voltages to be stored in the memory cell range from 0 to 4 volts. In order to use the memory cell as a two-bit memory cell, the voltage range is first divided into four distinct voltage sub-ranges: (1) 0 to 1 volt; (2) 1 to 2 volts; (3) 2 to 3 volts; and (4) 3 to 4 volts. Each voltage sub-range represents a certain combination of two data bits. For example, the first sub-range can represent the data bits "00", the second sub-range can represent the data bits "01", the third sub-range can represent the data bits "10", and the fourth sub-range can represent the dam bits "11". Once the voltage range is subdivided in this manner, two-bit data can be stored in the memory cell by applying and storing an appropriate voltage in the cell. For example, the data bits "10" can be stored in the memory cell by storing a voltage between 2 and 3 volts in the memory cell. Likewise, the data bits "11" can be stored in the memory cell by storing a voltage between 3 and 4 volts in the memory cell. Thus, by dividing the full voltage range into voltage sub-ranges, and then storing appropriate voltage levels in the memory cell, a single-bit memory cell can be converted into a multi-bit memory cell. This same concept can be extended to store three or more data bits per cell. In general, to store an n number of bits in a single cell, 2.sup.n distinct voltage sub-ranges will need to be created.
Storing data in a multi-bit memory cell is only one part of creating a practicable multi-bit memory. The other important consideration is that of reading data from the cells. In the prior art, two different reading methodologies have been implemented. According to a first reading methodology, commonly known as the serial A/D conversion method, data is read from a multi-bit memory cell by repeatedly comparing the voltage stored in the memory cell with a stepped reference voltage. More specifically, with each clock cycle, the reference voltage is increased by a certain step and then compared with the voltage stored in the memory cell. By comparing the stored voltage with all of the possible voltages which could be stored in the cell, the data stored in the cell is ascertained. This method is advantageous in that it requires little additional circuitry. However, it has proven to be quite slow. In general, to read n-bits of data from a cell, 2.sup.n clock cycles are required. For cells which store a relatively large number of bits (four bits, for example), this reading method is too slow to be practicable.
Another reading method which has been implemented in the prior art is commonly known as the flash A/D conversion method. According to this method, each cell is connected to 2.sup.n comparators, where n is the number of data bits stored in the cell. Each comparator has one input connected to the output of the cell, and another input connected to a reference voltage. Each of the comparators is connected to a different reference voltage. Data is read from the cell by outputting the voltage stored in the cell to the comparators, and allowing the comparators to compare, simultaneously, the stored voltage to each of the different reference voltages. By so doing, the voltage, and hence, the data stored in the cell is ascertained in a single clock cycle. While this method is significantly faster than the serial conversion method, it has a significant drawback in that it requires a large number of wire connections and a large number of comparators. More specifically, in order to implement the flash conversion method, there needs to be 2.sup.n wire connections for each cell to connect each cell to 2.sup.n comparators. These connections and comparators consume a very significant amount of surface area on a memory chip. For a memory having a large number of cells, the additional connections and comparators would consume the surface area saved by having multi-bit cells. Thus, a multi-bit memory using the flash conversion method would not provide increased storage density. As shown by this discussion, the reading methodologies of the prior art fail to provide satisfactory results. Thus, there exists a need for an improved reading methodology which would allow for faster reading times but which does not require an overly burdensome amount of additional circuitry.